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[Communication] 伪随机序列

Description: 线形反馈移位寄存器（LFSR)是数字系统中一个重要的结构，本程序可以自动产生AHDL,VHDL,Verilog的源代码及电路原理图。程序可以运行在win98/2000/NT平台-linear feedback shift register (LFSR) digital system is an important structure, the process can be automatically generated AHDL, VHDL, Verilog source code and circuit schematics. Procedures can run on platforms win98/2000/NT
Platform: | Size: 163107 | Author: 夏沫 | Hits:

[Communication] 伪随机序列

Description: 线形反馈移位寄存器（LFSR)是数字系统中一个重要的结构，本程序可以自动产生AHDL,VHDL,Verilog的源代码及电路原理图。程序可以运行在win98/2000/NT平台-linear feedback shift register (LFSR) digital system is an important structure, the process can be automatically generated AHDL, VHDL, Verilog source code and circuit schematics. Procedures can run on platforms win98/2000/NT
Platform: | Size: 162816 | Author: 夏沫 | Hits:

[Program doc] m序列发生器

Description: m序列发生器(简单型码序列发生器-----simple shift register generator)-m sequence generator (a simple code sequence generator----- simple shift Regi ster generator)
Platform: | Size: 3072 | Author: | Hits:

[Other] SC-DSC

Description: 数字通信系统的设计及其性能和所传输的数字信号的统计特性有关。所谓 加扰技术，就是不增加多余度而扰乱信号，改变数字信号的统计特性，使其近 似于白噪声统计特性的一种技术。这种技术的基础是建立在反馈移位寄存器序 列（伪随机序列）理论之上的。解扰是加扰的逆过程，恢复原始的数字信号。 如果数字信号具有周期性，则信号频谱为离散的谱线，由于电路的非线 性，在多路通信系统中，这些谱线对相邻信道的信号造成串扰。而短周期信号 经过扰码器后，周期序列变长，谱线频率变低，产生的非线性分量落入相邻信 道之外，因此干扰减小。 在有些数字通信设备中，从码元“0”和“1”的交变点提取定时信息，若 传输的数字信号中经常出现长的“1”或“0”游程，将影响位同步的建立和保 持。而扰码器输出的周期序列有足够多的“0”、“1”交变点，能够保证同步 定时信号的提取。 -digital communication system design and performance and the transmission of digital signals on the statistical characteristics. The so-called scrambling technology is not to increase the degree to disrupt redundant signal, digital signal change the statistical properties it is similar to white noise statistical characteristics of a technology. This technology is based on feedback shift register sequences (pseudo-random sequence) of the above theory. Decryption is the reverse of the scrambling process, the restoration of the original digital signal. If the digital signal is cyclical, the signal spectrum of discrete lines, as the nonlinear circuit, in multi-channel communication system, these lines of the adjacent channel signal causing crosstalk. And the short-cycle signal after scrambling
Platform: | Size: 113664 | Author: 葛岭泉 | Hits:

[VHDL-FPGA-Verilog] spi

Description: VHDL实现SPI功能源代码 -- The SPI bus is a 3 wire bus that in effect links a serial shift -- register between the "master" and the "slave". Typically both the -- master and slave have an 8 bit shift register so the combined -- register is 16 bits. When an SPI transfer takes place, the master and -- slave shift their shift registers 8 bits and thus exchange their 8 -- bit register values.-SPI realize the functional VHDL source code The SPI bus is a 3 wire bus that in effect links a serial shift register between the
Platform: | Size: 65536 | Author: 阿飞 | Hits:

[VHDL-FPGA-Verilog] encoder

Description: VHDL实现循环码编码，设计了三个单元。switch是一个开关，shifter是移位寄存器，encoder是主体。-VHDL realization of cyclic code encoding, designed three modules. switch is a switch, shifter is the shift register, encoder is the main.
Platform: | Size: 2048 | Author: 王三一 | Hits:

[VHDL-FPGA-Verilog] LFSR

Description: 自动生成线形反馈移位寄存器的各种HDL源代码和原理图的工具-Automatic generation of linear feedback shift register of a variety of HDL source code and schematic tools
Platform: | Size: 162816 | Author: zx | Hits:

[VHDL-FPGA-Verilog] shiftdata

Description: 双向移位寄存器的VHDL源程序,自己做实验编写的可以用 谢谢大家-Bi-directional shift register of the VHDL source code, prepared by their own experiments can be used Thank you
Platform: | Size: 1024 | Author: 朱武增 | Hits:

[VHDL-FPGA-Verilog] fcsr

Description: 伪随机序列产生器－代进位反馈移位寄存器，verilog hdl 原代码。-Pseudo-random sequence generator- on behalf of binary feedback shift register, verilog hdl original code.
Platform: | Size: 1024 | Author: 李辛 | Hits:

[VHDL-FPGA-Verilog] RL_SHIFT

Description: 带有同步预置的加载左右移位寄存器VHDL源代码-With synchronous preset load shift register about VHDL source code
Platform: | Size: 150528 | Author: sunrier | Hits:

[Other Embeded program] ShiftRegister

Description: Shift register verilog code
Platform: | Size: 1024 | Author: selcuk | Hits:

[Documents] project

Description: synthesizable code for shift register of user defined size
Platform: | Size: 3072 | Author: krupal | Hits:

[VHDL-FPGA-Verilog] par_serial-and-serial_par-VHDL

Description: 并入串出移位寄存器和8路并行输出串行移位寄存器的VHDL代码，经Quartus II 5.1验证可用-String into a shift register and 8-way parallel output serial shift register of the VHDL code, the Quartus II 5.1 can be used to verify
Platform: | Size: 1024 | Author: 随风 | Hits:

[VHDL-FPGA-Verilog] shiftregister

Description: Shift Register. VHDL code and its testbench.
Platform: | Size: 1024 | Author: mehmet | Hits:

[VHDL-FPGA-Verilog] RSC

Description: Turbo码编码器的两个分量编码器RSC，主要由四个移位寄存器和两个模2加法器组成-Turbo code encoder of the two component encoders RSC, mainly by the four shift register and the two-mode adder composed of 2
Platform: | Size: 1024 | Author: sunhao | Hits:

[VHDL-FPGA-Verilog] mux_reg

Description: VHDL code for a multiplexer and a parallel/serial in parallel/serial out shift register
Platform: | Size: 1024 | Author: Davood | Hits:

[VHDL-FPGA-Verilog] VHDL-test-code-8-bit-shift-register

Description: VHDL实验代码：8位移位寄存器，这是一个基于VHDL的8位寄存器，非常实用的一个小程序-VHDL test code: 8-bit shift register, which is a VHDL-based 8-bit registers, a very useful little program
Platform: | Size: 1024 | Author: Johonson | Hits:

[VHDL-FPGA-Verilog] shft_reg_8_vhdl

Description: this a shift register vhdl code-this is a shift register vhdl code
Platform: | Size: 1024 | Author: yz | Hits:

[VHDL-FPGA-Verilog] VHDL

Description: VHDL小程序，其中包含了bcd码转换成格雷码、寄存器的简单设计（并入串出移位寄存器、串入串出移位寄存器）以及脉冲发生器的VHDL实现。适合于基础的VHDL入门。-VHDL small program, which includes a bcd code into Gray code, register for a simple design (String into a shift register, the string into the string out of the shift register) and a pulse generator VHDL implementation. Suitable for basic VHDL entry.
Platform: | Size: 304128 | Author: 鸿雨 | Hits:

[Other] LFSR

Description: Linear-feedback shift register vhdl code
Platform: | Size: 25600 | Author: mahdi | Hits:
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